1. Field of the Invention
The present invention relates to a method and apparatus for driving a display panel, and more particularly, to a method and apparatus for driving a display panel in which a bus link between a timing controller and a source driver block is altered in order to simplify the structure of a circuit.
2. Description of the Related Art
Korean Patent Laid-Open Publication No. 2005-0064568 and U.S. Pat. No. 6,665,742 that are related to the present invention were disclosed.
FIG. 1 is a circuit diagram of a conventional apparatus 100 for driving a display panel 110, such as a liquid crystal display (LCD) panel. Referring to FIG. 1, the conventional apparatus 100 for driving the display panel 110 typically comprises the display panel 110, a printed circuit board (PCB) 130, which provides a place to mount a timing controller 120, and a film 140 that couples the display panel 110 and the PCB 130. Three source drivers SD1, SD2, and SD3 for driving the display panel 110 are mounted on the film 140.
In a bus link illustrated in FIG. 1, the timing controller 120 transmits data D1, D2, and D3 and control signals CLK, DIO, and IREF to the first source driver SD1. A power line and a gamma signal line are coupled to all the source drivers SD1, SD2, and SD3.
After receiving the data D1, D2, and D3 and control signals CLK, DIO, and IREF, the first source driver SD1 transmits data D2 and D3 and control signals CLK, DIO2, and IREF to the second source driver SD2 through buses that are cascaded together.
After receiving the data D2 and D3 and control signals CLK, DIO2, and IREF, the second source driver SD2 transmits data D3 and control signals CLK, DIO3, and IREF to the third source driver SD3 through buses that are cascaded together.
In order to transmit signals according to the bus link of FIG. 1, each source driver needs a transmission circuit to transmit data and control signals to source drivers that are cascaded together, and a reception circuit to receive the data and control signals. This, however, increases the area of source drivers and power consumption. Furthermore, each source driver additionally needs a delay locked loop (DLL) circuit to reproduce a clock signal necessary for the transmission of the data and control signals.